View HI3-0506A-5_217889.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HI-506A, HI-507A, HI-508A, HI-509A
Data Sheet June 1999 File Number 3143.2
16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel, CMOS Analog MUXs with Active Overvoltage Protection
The HI-506A, HI-507A, HI-508A and HI-509A are analog multiplexers with active overvoltage protection. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70VP-P levels with 15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1k of resistance under this condition. These features make the HI-506A, HI-507A, HI-508A and HI-509A ideal for use in systems where the analog inputs originate from external equipment, or separately powered circuitry. All devices are fabricated with 44V dielectrically isolated CMOS technology. The HI-506A is a single 16-Channel multiplexer, the HI-507A is an 8-Channel differential multiplexer, the HI-508A is a single 8-Channel multiplexer and the HI-509A is a differential 4-Channel multiplexer. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application Notes AN520 and AN521.
Features
* Analog Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . 70VP-P * No Channel Interaction During Overvoltage * Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . . 44V * Fail Safe with Power Loss (No Latch-Up) * Break-Before-Make Switching * Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . 15V * Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns * Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mW
Applications
* Data Acquisition Systems * Industrial Controls * Telemetry
Ordering Information
PART NUMBER HI1-0506A-2 HI1-0506A-5 HI1-0506A-8 HI3-0506A-5 HI1-0507A-8 HI3-0507A-5 HI1-0508A-7 HI1-0508A-8 HI3-0508A-5 HI1-0509A-2 HI1-0509A-5 HI1-0509A-8 HI3-0509A-5 TEMP. RANGE (oC) -55 to 125 0 to 75 PACKAGE 28 Ld CERDIP 28 Ld CERDIP PKG. NO. F28.6 F28.6 F28.6 E28.6 F28.6 E28.6 F16.3 F16.3 E16.3 F16.3 F16.3 F16.3 E16.3
-55 to 125 28 Ld CERDIP + 160 Hour Burn-In 0 to 75 28 Ld PDIP
-55 to 125 28 Ld CERDIP + 160 Hour Burn-In 0 to 75 28 Ld PDIP
0 to 75 16 Ld CERDIP + 96 Hour Burn-In -55 to 125 16 Ld CERDIP + 160 Hour Burn-In +0 to 75 -55 to 125 0 to 75 16 Ld PDIP 16 Ld CERDIP 16 Ld CERDIP
-55 to 125 16 Ld CERDIP + 160 Hour Burn-In 0 to 75 16 Ld PDIP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
HI-506A, HI-507A, HI-508A, HI-509A Pinouts
HI-506A (CERDIP, PDIP) TOP VIEW
+VSUPPLY 1 NC 2 NC 3 IN 16 4 IN 15 5 IN 14 6 IN 13 7 IN 12 8 IN 11 9 IN 10 10 IN 9 11 GND 12 VREF 13 ADDRESS A3 14 28 OUT 27 -VSUPPLY 26 IN 8 25 IN 7 24 IN 6 23 IN 5 22 IN 4 21 IN 3 20 IN 2 19 IN 1 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2
HI-507A (CERDIP, PDIP) TOP VIEW
+VSUPPLY 1 OUT B 2 NC 3 IN 8B 4 IN 7B 5 IN 6B 6 IN 5B 7 IN 4B 8 IN 3B 9 IN 2B 10 IN 1B 11 GND 12 VREF 13 NC 14 28 OUT A 27 -VSUPPLY 26 IN 8A 25 IN 7A 24 IN 6A 23 IN 5A 22 IN 4A 21 IN 3A 20 IN 2A 19 IN 1A 18 ENABLE 17 ADDRESS A0 16 ADDRESS A1 15 ADDRESS A2
HI-508A (CERDIP, PDIP) TOP VIEW
A0 1 ENABLE 2 -VSUPPLY 3 IN 1 4 IN 2 5 IN 3 6 IN 4 7 OUT 8 16 A1 15 A2 14 GND 13 +VSUPPLY 12 IN 5 11 IN 6 10 IN 7 9 IN 8
HI-509A (CERDIP, PDIP) TOP VIEW
A0 1 ENABLE 2 -VSUPPLY 3 IN 1A 4 IN 2A 5 IN 3A 6 IN 4A 7 OUT A 8 16 A1 15 GND 14 +VSUPPLY 13 IN 1B 12 IN 2B 11 IN 3B 10 IN 4B 9 OUT B
2
HI-506A, HI-507A, HI-508A, HI-509A Truth Tables
HI-506A A3 X L L L L L L L L H H H H H H H H A2 X L L L L H H H H L L L L H H H H A1 X L L H H L L H H L L H H L L H H A0 X L H L H L H L H L H L H L H L H EN L H H H H H H H H H H H H H H H H "ON" CHANNEL None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A1 X L L H H A0 X L H L H HI-509A EN L H H H H "ON" CHANNEL PAIR None 1 2 3 4 A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H HI-508A EN L H H H H H H H H "ON" CHANNEL None 1 2 3 4 5 6 7 8
HI-507A A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H EN L H H H H H H H H "ON" CHANNEL PAIR None 1 2 3 4 5 6 7 8
3
HI-506A, HI-507A, HI-508A, HI-509A Functional Diagrams
HI-506A
1K IN 1A 1K IN 8A DECODER/ DRIVER 1K IN 16 IN 8B OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT 1K DECODER/ DRIVER 1K IN 1B OUT B
HI-507A
OUT A
1K IN 1 1K IN 2
OUT
DIGITAL INPUT
PROTECTION VREF A0 A1 A2 A3 EN
DIGITAL INPUT
PROTECTION
VREF A0
A1
A2
EN
HI-508A
1K IN 1A 1K IN 4A DECODER/ DRIVER 1K IN 8 IN 4B OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 1K 1K IN 1B
HI-509A
OUT A
1K IN 1 1K IN 2
OUT
OUT B
DECODER/ DRIVER
DIGITAL INPUT
PROTECTION A0
5V REF
LEVEL SHIFT
A1
A2
EN
DIGITAL INPUT
PROTECTION A0
A1
EN
4
HI-506A, HI-507A, HI-508A, HI-509A Schematic Diagrams
ADDRESS INPUT BUFFER AND LEVEL SHIFTER
TTL REFERENCE CIRCUIT V+
R10 R9 VREF Q1 Q4 D3 GND LEVEL SHIFTER V+ P P P P P P P P P
OVERVOLTAGE PROTECTION V+ D2
P
N
R2 R5 R3 N N R4 R6 N N N N R8 N N R7
LEVEL SHIFTED ADDRESS TO DECODE
R1 200
D1
N GND V-
VADD IN
ADDRESS DECODER
V+
P
P
P
P
P
P
P
N A0 OR A0 A1 OR A1
N
N
TO P-CHANNEL DEVICE OF THE SWITCH
N
N
A2 OR A2
TO N-CHANNEL DEVICE OF THE SWITCH
N
A3 OR A3
N
ENABLE DELETE A3 OR A3 INPUT FOR HI-507A, HI-508A, HI-509A DELETE A2 OR A2 INPUT FOR HI-509A
V-
5
HI-506A, HI-507A, HI-508A, HI-509A Schematic Diagrams
(Continued) MULTIPLEX SWITCH
FROM DECODE OVERVOLTAGE PROTECTION N
V+ P Q5
R11 1K IN
D6
D7
D4
D5
N OUT
N Q6
VP FROM DECODE
6
HI-506A, HI-507A, HI-508A, HI-509A
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Digital Input Voltage (VEN , VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V or 20mA, Whichever Occurs First Analog Signal (VIN, VOUT). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, IN or OUT, Pulsed 1ms, 10% Duty Cycle (Max). . 40mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) 28 Ld CERDIP Package. . . . . . . . . . . . 55 18 16 Ld CERDIP Package. . . . . . . . . . . . 85 32 28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A 16 Ld PDIP Package . . . . . . . . . . . . . . 90 N/A Maximum Junction Temperature CERDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Ranges HI-506A/507A/508A/509A-2, -8 . . . . . . . . . . . . . . -55oC to 125oC HI-506A/507A/508A/509A-5, -7 . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section TEST CONDITIONS TEMP (oC) -2, -8 MIN TYP MAX MIN -5, -7 TYP MAX UNITS
PARAMETER DYNAMIC CHARACTERISTICS Access Time, tA
Note 2
25 Full
25 -
0.5 80 300 300 -
1.0 500 1000 500 1000
25 -
0.5 80 300 300 -
1.0 1000 1000
s s ns ns ns ns ns s s s s dB pF
Break-Before-Make Delay, tOPEN Enable Delay (ON), tON(EN)
Note 2 Note 2
25 25 Full
Enable Delay (OFF), tOFF(EN)
Note 2
25 Full
Settling Time, tS HI-506A and HI-507A To 0.1% To 0.01% HI-508A and HI-509A To 0.1% To 0.01% Off Isolation Channel Input Capacitance, CS(OFF) Channel Output Capacitance, CD(OFF) HI-506A HI-507A HI-508A HI-509A Digital Input Capacitance, CA Input to Output Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold, TTL Drive, VAL Input High Threshold, VAH (Note 9) Input Leakage Current (High or Low), IA Note 2 Note 2 Notes 2, 6 Full Full Full 4.0 0.8 1.0 4.0 0.8 1.0 V V A 25 25 25 25 25 25 52 30 25 12 10 0.1 52 30 25 12 10 0.1 pF pF pF pF pF pF Note 7 25 25 25 25 25 25 50 1.2 3.5 1.2 3.5 68 10 50 1.2 3.5 1.2 3.5 68 10 -
7
HI-506A, HI-507A, HI-508A, HI-509A
Electrical Specifications
Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued) TEST CONDITIONS VREF = +10V VREF = +10V TEMP (oC) 25 25 -2, -8 MIN 6.0 TYP MAX 0.8 MIN 6.0 -5, -7 TYP MAX 0.8 UNITS V V
PARAMETER MOS Drive, VAL , HI-506A/HI-507A MOS Drive, VAH , HI-506A/HI-507A ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN On Resistance, rON
Note 2 Notes 2, 3
Full 25 Full
-15 -
1.2 1.5 0.03 0.1 4.0 0.1 -
+15 1.5 1.8 50 300 200 200 100 2.0 300 200 200 100 50
-15 -
1.5 1.8 0.03 0.1 4.0 0.1 -
+15 1.8 2.0 50 300 200 200 100 300 200 200 100 50
V k k nA nA nA nA nA nA nA nA A nA nA nA nA nA nA
Off Input Leakage Current, IS(OFF)
Notes 2, 4
25 Full
Off Output Leakage Current, ID(OFF) HI-506A HI-507A HI-508A HI-509A ID(OFF) With Input Overvoltage Applied
Notes 2, 4
25 Full Full Full Full
Note 5
25 Full
On Channel Leakage Current, ID(ON) HI-506A HI-507A HI-508A HI-509A Differential Off Output Leakage Current, IDIFF , (HI-507A, HI-509A Only) POWER SUPPLY CHARACTERISTICS Current, I+ Current, IPower Dissipation, PD NOTES:
Notes 2, 4
25 Full Full Full Full Full
Notes 2, 8 Notes 2, 8
Full Full Full
-
0.5 0.02 7.5
2.0 1.0 -
-
0.5 0.02 7.5
2.0 1.0 -
mA mA mW
2. 100% tested for Dash 8. Leakage currents not tested at -55oC. 3. VOUT = 10V, IOUT = +100A. 4. 10nA is the practical lower limit for high speed measurement in the production test environment. 5. Analog Overvoltage = 33V. 6. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC. 7. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS , f = 100kHz. 8. VEN , VA = 0V or 4V. 9. To drive from DTL/TTL Circuits, 1k pull-up resistors to +5V supply are recommended.
8
HI-506A, HI-507A, HI-508A, HI-509A Test Circuits and Waveforms
TA = 25oC, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified
100A
V2
IN
OUT V2 100A
VIN
rON =
FIGURE 1A. TEST CIRCUIT
1.4 NORMALIZED RESISTANCE (REFERRED TO VALUE AT 15V) 1.3 ON RESISTANCE (k) 1.2 1.1 25oC 1.0 0.9 0.8 0.7 0.6 -10 -55oC 125oC 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 -8 -6 -4 -2 0 2 4 ANALOG INPUT (V) 6 8 10 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE (V) -55oC TO 125oC VIN = +5V
FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE
FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 1. ON RESISTANCE
100nA
10nA LEAKAGE CURRENT OFF OUTPUT CURRENT ID(OFF) EN OUT +0.8V
ON LEAKAGE CURRENT ID(ON) 1nA
A
ID(OFF)
100pA
OFF INPUT LEAKAGE CURRENT IS(OFF)
10pA
25
50
75
100
125
TEMPERATURE (oC)
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE
FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 10)
9
10V
10V
HI-506A, HI-507A, HI-508A, HI-509A Test Circuits and Waveforms
TA = 25oC, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
OUT A IS(OFF) EN 10V +0.8V A0 A1 EN
OUT A ID(ON)
FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 10) NOTE:
10. Two measurements per channel: 10V and +10V. (Two measurements per device for ID(OFF) 10V and +10V.) FIGURE 2. LEAKAGE CURRENTS
18 ANALOG INPUT CURRENT (mA) 15 12 9 6 3 0 15 18 21 24 27 30 33 36 ANALOG INPUT OVERVOLTAGE (V) OUTPUT OFF LEAKAGE CURRENT ID(OFF) ANALOG INPUT CURRENT (IIN)
6 5 4 3 2 1 0
OUTPUT OFF LEAKAGE CURRENT (nA)
FIGURE 3A. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS
14 12 SWITCH CURRENT (mA) 10 8 6 4 2 0 0 2 4 6 8 10
FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4. ON CHANNEL CURRENT
10V
10V
10V
4V
FIGURE 2D. ID(On) TEST CIRCUIT (NOTE 10)
7
A
IIN
A
ID(OFF)
VIN
FIGURE 3B. TEST CIRCUIT
FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS
-55oC
25oC
125oC
VIN
A
12
14
VOLTAGE ACROSS SWITCH (V)
FIGURE 4B. TEST CIRCUIT
10
HI-506A, HI-507A, HI-508A, HI-509A Test Circuits and Waveforms
8 A
TA = 25oC, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
+15V/+10V +ISUPPLY
SUPPLY CURRENT (mA)
6
4
VSUPPLY = 15V VA VSUPPLY = 10V 50
V+ IN 1 HI-506A A2 IN 2 THRU A1 IN 7/IN 15 A3 A0 IN 8/IN 16 OUT V-
10V/5V
10V/
2
+4V
EN GND
10 M
0 1K 10K 100K TOGGLE FREQUENCY (Hz) 1M 10M
A -ISUPPLY -15V/-10V
FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY
Similar connection for HI-507A/HI-508A/HI-509A
FIGURE 5B. TEST CIRCUIT
FIGURE 5. DYNAMIC SUPPLY CURRENT
900 800 ACCESS TIME (ns) 700 600 500 +4V 400 300 3 4 5 6 7 9 10 11 12 8 LOGIC LEVEL (HIGH) (V) 13 14 15 VA 50 VREF = OPEN FOR LOGIC HIGH LEVEL 6V VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V A3 A2 A1 A0 EN GND VREF
+15V
V+ IN 1
10V
IN 2 THRU IN 7/IN 15 HI-506A IN 16 OUT V10V
10 k
-15V
FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH)
Similar connection for HI-507A/HI-580A/HI-509A
FIGURE 6B. TEST CIRCUIT
VAH = 4.0V
1/ V 2 AH
ADDRESS DRIVE (VA) 0V
VA INPUT 2V/DIV. S1 ON
+10V OUTPUT 10% tA
OUTPUT 5V/DIV.
-10V
S16 ON 200ns/DIV.
FIGURE 6C. MEASUREMENT POINTS FIGURE 6. ACCESS TIME
FIGURE 6D. WAVEFORMS
11
5V
14 pF
50 pF
HI-506A, HI-507A, HI-508A, HI-509A Test Circuits and Waveforms
TA = 25oC, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
A3 A2
HI-506A IN 1 IN 2 THRU
+5V VAH = 4.0V
VA
50
A1 A0
IN 7/IN 15 IN 8/IN 16 OUT GND VOUT 1k 50pF 50% 50% 0V
ADDRESS DRIVE (VA)
+4.0V
EN
OUTPUT
Similar connection for HI-507A/HI-508A/HI-509A
FIGURE 7A. TEST CIRCUIT
tOPEN
FIGURE 7B. MEASUREMENT POINTS
VA INPUT 2V/DIV.
S1 ON
S16 ON
OUTPUT 0.5V/DIV.
100ns/DIV.
FIGURE 7C. WAVEFORMS FIGURE 7. BREAK-BEFORE-MAKE DELAY
12
HI-506A, HI-507A, HI-508A, HI-509A Test Circuits and Waveforms
TA = 25oC, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
A3 A2
HI-506A IN 1 IN 2 THRU IN 7/IN 15 IN 8 /IN 16 +10V VAH = 4.0V 50% 50% ENABLE DRIVE (VA) 0V OUT GND 1k VOUT 50pF
A1 A0 EN VA 50
90% OUTPUT 10% 0V tON(EN)
Similar connection for HI-507A//HI-508A/HI-509A
FIGURE 8A. TEST CIRCUIT
tOFF(EN)
FIGURE 8B. MEASUREMENT POINTS
ENABLE DRIVE 2V/DIV.
DISABLED
ENABLED (S1 ON)
OUTPUT 2V/DIV.
100ns/DIV.
FIGURE 8C. WAVEFORMS FIGURE 8. ENABLE DELAYS
13
HI-506A, HI-507A, HI-508A, HI-509A Die Characteristics
DIE DIMENSIONS: 159 mils x 83.9 mils METALLIZATION: Type: CuAl Thickness: 16kA 2kA SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Silox: 12kA 2kA Nitride: 3.5kA 1kA
NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential.
WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 TRANSISTOR COUNT: 485 PROCESS: CMOS-DI
Metallization Mask Layouts
HI-506A
EN (18) A0 (17) A1 A2 (16) (15) A3 VREF (14) (13) GND (12) EN (18) A0 (17)
HI-507A
A1 A2 (16) (15) NC VREF (14) (13) GND (12)
IN 1 (19) IN 2 (20)
IN 9 (11) IN 10 (10)
IN 1A (19) IN 2A (20)
IN 1B (11) IN 2B (10)
IN 3 (21) IN 4 (22)
IN 11 (9) IN 12 (8)
IN 3A (21) IN 4A (22)
IN 3B (9) IN 4B (8)
IN 5 (23) IN 6 (24)
IN 13 (7) IN 14 (6)
IN 5A (23) IN 6A (24)
IN 5B (7) IN 6B (6)
IN 7 (25) IN 8 (26)
IN 15 (5) IN 16 (4)
IN 7A (25) IN 8A (26)
IN 7B (5) IN 8B (4)
V- (27)
OUT (28)
+V (1)
NC (2)
V- (27)
OUT A (28)
+V (1)
OUT B(2)
14
HI-506A, HI-507A, HI-508A, HI-509A Die Characteristics
DIE DIMENSIONS: 108 mils x 83 mils METALLIZATION: Type: CuAl Thickness: 16kA 2kA SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Silox: 12kA 2kA Nitride: 3.5kA 1kA
NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential.
WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 TRANSISTOR COUNT: 253 PROCESS: CMOS-DI
Metallization Mask Layouts
HI-508A HI-509A
IN 6 (11)
IN 7 IN 8 (10) (9)
OUT (8)
IN 4 IN 3 (7) (6)
IN 3B IN 4B OUT B (11) (10) (9)
OUT A (8)
IN 4A IN 3A (7) (6)
IN 5 (12) +V (13) GND (14)
IN 2 (5) IN 1 (4) -V (3)
IN 2B (12) IN 1B (13) +V (14)
IN 2A (5) IN 1A (4) -V (3)
A2 (15)
A1 (16)
A0 (1)
EN (2)
GND (15)
A1 (16)
A0 (1)
EN (2)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 15

▲Up To Search▲

Price & Availability of HI3-0506A-5

	To Download HI3-0506A-5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .